The present invention relates to a method of fabricating a semiconductor device.
Metal oxide semiconductor (MOS) transistors are used in various kinds of semiconductor devices. As one of semiconductor memory devices, a dynamic random access memory (DRAM) includes a plurality of unit cells each having one transistor and one capacitor. A MOS transistor includes a gate insulating layer and a gate electrode, which are sequentially formed on a substrate having impurity regions, e.g., a source region and a drain region. A channel region is defined between the impurity regions. When a bias voltage is applied to the gate electrode, an inversion layer is formed in the channel region and carriers move through the inversion layer.
As a semiconductor device becomes more highly integrated, the transistor is scaled down and the channel length of the transistor is reduced. It is well known that the performance of the transistor is degraded due to a short channel effect caused by the reduced channel length. Various methods have been used for suppressing the short channel effect. One method is to form a shallow impurity region in a substrate. In forming the shallow impurity region, the implantation depth of impurity ions must be reduced during impurity ion implantation. In addition, the dose of the impurity ions to be implanted must be reduced. A tilt implantation method has been recently used to implant impurity ions at a tilt angle of, e.g., 7 degrees instead of 0 degree.
The shallow ion implantation method is vulnerable to dopant loss at a surface or junction interface whereby the implanted impurity ions are not sufficiently diffused. Hence, sheet resistance within the impurity region increases. In addition, when the dose for the shallow impurity region is reduced, an amount of activated dopants is reduced and thus the sheet resistance further increases. Moreover, dopant loss may also occur at the gate insulating layer by a thermal treatment performed after the ion implantation for the formation of the impurity region. This dopant loss occurs more seriously in a recess gate structure adopted for suppressing the short channel effect. That is, the dopant loss occurs in a recess etching process of forming the recess gate structure and the dopant loss occurs in sidewalls of the recess gate during a subsequent thermal treatment. The dopant loss increases the sheet resistance within the impurity region, degrading the performance of the transistor.